Greetings
We are Hiring Senior IP Design Engineer - System Verilog RTL
London, UK OR Belfast, NI. (Person must be willing to travel to Belfast once OR twice in a quarter)
6 Months.
1-2 Days (Flexible Hybrid).
6 Months Fixed Term. (Possible Extension)
DOE
Core Scope:
Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing an...